1. Field of the Invention
The present invention relates to a high frequency switch provided in a high frequency circuit section of a transmitting section of a mobile communication terminal such as a portable telephone terminal and used for switching the signal path of a high frequency signal.
The invention further relates to an amplifying circuit for switching the signal path of a high frequency signal and, at the same time, amplifying the high frequency signal.
The invention further relates to a mobile communication terminal provided with the high frequency switch or the amplifying circuit mentioned above.
In particular, the invention relates to a high frequency switch and an amplifying circuit for switching the signal path of a high frequency signal in response to a control voltage.
2. Description of the Related Art
A recent major trend in the field of mobile communication is that a plurality of communication schemes are integrated in an integrated portable telephone terminal. An example of this is a portable telephone terminal which supports both W-CDMA (wide band code division multiple access) scheme and PDC (personal digital cellular) scheme. Such an integrated portable telephone terminal provides the advantages of both schemes, such as a high data communication speed obtained in W-CDMA scheme and a wide service area available in PDC scheme, and is thereby expected to spread rapidly in the future.
Nevertheless, the frequency used as the carrier wave is different in W-CDMA scheme and in PDC scheme. Thus, two separate sub-blocks for W-CDMA scheme and PDC scheme need to be provided in the high frequency circuit block. Further, in order to reduce the size of the mobile communication terminal and the operation current of the high frequency circuit block, the design of the high frequency circuit block becomes more important.
Described below is a typical prior art portable telephone terminal which supports a plurality of communication schemes such as PDC and W-CDMA.
FIG. 4 is a block diagram showing the configuration of a radio section of a typical prior art portable telephone terminal. In FIG. 4, the radio section of the portable telephone terminal comprises a transmitting section 200, a receiving section 300, a synthesizer section 400, and a shared device section 500.
The transmitting section 200 comprises: an up converter 201 for converting a modulated signal input (intermediate frequency modulated signal) having an intermediate frequency (such as 600 MHz) into a signal having a transmission frequency (approximately 900 MHz in PDC scheme and approximately 1.9 GHz in W-CDMA scheme); a variable gain high frequency amplifier circuit 202 for amplifying the output signal (1 mW or lower) of the up converter 201 into 10 mW or the like at maximum; a high frequency switch 203 for switching a band pass filter to be used, depending on the transmission frequency; a band pass filter 204 and a band pass filter 207 for extracting a signal in the transmission wave band; a fixed gain high power high frequency amplifier circuit 205 for amplifying the high frequency signal (10 mW or lower) outputted from the band pass filter 204 into 1 W or the like at maximum; an isolator 206 for providing the output of the high power high frequency amplifier circuit 205 to the shared device section 500 for transmitting the output as a radio wave; a fixed gain high power high frequency amplifier circuit 208 for amplifying the high frequency signal (10 mW or lower) outputted from the band pass filter 207 into 1 W or the like at maximum; an isolator 209 for providing the output of the high power high frequency amplifier circuit 208 to the shared device section 500 for transmitting the output as a radio wave.
The receiving section 300 comprises: a front end IC 301 for performing the high frequency amplification of a reception signal received by the shared device section 500 and then mixing this reception signal with a local oscillation signal provided from the synthesizer section 400; and a band pass filter 302 for extracting an intermediate frequency signal from the output signal of the front end IC 301.
The synthesizer section 400 comprises a temperature controlled quartz oscillator (TCXO) 401, a phase locked loop (PLL) circuit 402, and a voltage controlled oscillator (VCO) 403.
The shared device section 500 comprises an antenna 501, an antenna 502, and a duplexer 503.
In order that a plurality of communication schemes such as PDC and W-CDMA are supported and that the size of the high frequency circuit block is still reduced in the mobile communication terminal, the up converter 201 and the high frequency amplifier circuit 202 are shared for both communication schemes in this radio section. In contrast, the band pass filters 204 and 207, the high power high frequency amplifier circuits 205 and 208, and isolators 206 and 209 are arranged in separate circuit sub-blocks necessary for the respective communication frequencies. This causes the necessity of the high frequency switch 203 for selecting the circuit sub-block depending on the communication frequency.
FIG. 5 is a block diagram showing the configuration of a radio section of another prior art portable telephone terminal. In FIG. 5, a signal input terminal 101 receives an intermediate frequency modulated signal generated by the modulation of voice and the like. An up converter 103 receives the intermediate frequency modulated signal from the signal input terminal 101 and a local oscillation signal from an oscillator 102. The up converter 103 then converts the intermediate frequency into a transmission frequency. More specifically, the up converter 103 mixes the signal (intermediate frequency modulated signal) having the intermediate frequency with the local oscillation signal from the oscillator 102, and thereby converts the intermediate frequency into the transmission frequency.
Here, the frequency of the intermediate frequency modulated signal inputted to the up converter 103 is denoted by fif. The local oscillation frequency of the oscillator 102 is denoted by flo. The frequency of the transmission signal is denoted by fc. At this time, the relationfc=flo±fifholds among the frequency of the transmission signal, the frequency of the intermediate frequency modulated signal, and the local oscillation frequency. Thus, the up converter 103 outputs a transmission signal having a frequency of fc. Examples of the intermediate frequency and the transmission signal frequency are described above. When the oscillation frequency of the oscillator 102 is changed, transmission waves corresponding to a plurality of transmission frequencies, such as those used in PDC scheme and W-CDMA scheme, can be synthesized.
A high frequency amplifier circuit 104 is provided with the function of gain control, and thereby amplifies a signal having the transmission frequency into 10 mW or the like at maximum. A high frequency switch 105 selects a high frequency circuit corresponding to the communication frequency.
In the present example, the high frequency circuit composed of a band pass filter 106, a high power high frequency amplifier circuit 107, and an isolator 108 is defined as that used in PDC scheme. The high frequency circuit composed of a band pass filter 109, a high power high frequency amplifier circuit 110, and an isolator 111 is defined as that used in W-CDMA scheme.
In PDC scheme, the output signal of the high frequency amplifier circuit 104 is outputted from a terminal 105a to a terminal 105b of the high frequency switch 105, and thereby provided to the band pass filter 106. The band pass filter 106 extracts solely a signal in the transmission wave band from the inputted signal, and then outputs the signal. The high power high frequency amplifier circuit 107 amplifies the output signal (the signal having the transmission frequency) of the band pass filter 106 into 1 W or the like at maximum. The output of the high power high frequency amplifier circuit 107 is provided through the isolator 108 to a terminal 112a of a duplexer 112.
In W-CDMA scheme, the output signal of the high frequency amplifier circuit 104 is outputted from the terminal 105a to a terminal 105c of the high frequency switch 105, and thereby provided to the band pass filter 109. The band pass filter 109 extracts solely a signal in the transmission wave band from the inputted signal, and then outputs the signal. The high power high frequency amplifier circuit 110 amplifies the output signal (the signal having the transmission frequency) of the band pass filter 109 into 1 W or the like at maximum. The output of the high power high frequency amplifier circuit 110 is provided through the isolator 111 to a terminal 112b of the duplexer 112.
The duplexer 112 transfers the transmission signal outputted from the isolator 108 to the antenna 113, transfers the reception signal received by the antenna 113 to a signal output terminal 115, transfers the transmission signal outputted from the isolator 111 to the antenna 114, transfers the reception signal received by the antenna 114 to a signal output terminal 116.
In the high frequency circuit block of FIG. 5, the antenna 113 or 114 is selectively used depending on the communication scheme. The antenna 113 is used for PDC scheme, while the antenna 114 is used for W-CDMA scheme. More specifically, the duplexer 112 has the following function. That is, the signal from the terminal 112a is transmitted to the terminal 112c, whereas the signal from the terminal 112a is blocked to the other terminals. The signal from the terminal 112b is transmitted to the terminal 112d, whereas the signal from the terminal 112b is blocked to the other terminals. The signal from the terminal 112c is transmitted to the terminal 112e, whereas the signal from the terminal 112c is blocked to the other terminals. The signal from the terminal 112d is transmitted to the terminal 112f, whereas the signal from the terminal 112d is blocked to the other terminals. Further, the signals from the terminal 112e and the terminal 112f are blocked to the other terminals.
In the configuration of FIG. 5, the high frequency switch 105 has selected the high frequency circuit, whereby the size of the high frequency circuit block has been reduced in the mobile communication terminal such as a portable telephone terminal supporting a plurality of communication schemes. In order that the size of the high frequency circuit block is further reduced in the mobile communication terminal, the circuit block having been constructed from discrete elements such as the high frequency amplifier circuit and the high frequency switch needs to be integrated.
Described below is a high frequency switch used in a high frequency circuit block of a mobile communication terminal.
In a high frequency switch used in a high frequency circuit block, a MES FET has been used so that the ON resistance and the OFF resistance of the FET has implemented the switching function. In general, a MES FET is a depression type FET, and has a negative threshold voltage. When a high frequency switch is constructed from a MES FET, the source electrode and the drain electrode of the FET are used as two signal electrodes, while the gate electrode of the FET is used as a control electrode. When the source electrode and the drain electrode of the FET are set at 0 V, in order that the FET goes ON, the gate electrode can be set at 0 V. In order that the FET goes OFF, the gate electrode can be set at a voltage lower than the threshold.
FIG. 6 shows an SPDT (single pole dual through) switch circuit using FETS, which serves as a high frequency switch. In the SPDT switch circuit of FIG. 6, the source electrode of a field effect transistor 131 serving as a switching element is connected through a capacitor 151 to a signal input terminal 125, while the drain electrode of the field effect transistor 131 is connected through a capacitor 152 to a signal output terminal 127. Further, the source electrode of a field effect transistor 132 serving as a switching element is connected through a capacitor 153 to the signal input terminal 125, while the drain electrode of the field effect transistor 132 is connected through a capacitor 154 to a signal output terminal 128.
The source electrode of the field effect transistor 131 is connected through a resistor 141 to a control terminal 124. The gate electrode of the field effect transistor 132 is connected through a resistor 142 to the control terminal 124.
The source electrode and the drain electrode of the field effect transistor 131 are interconnected through a resistor 146, and thereby maintained at the same potential. The source electrode and the drain electrode of the field effect transistor 132 are interconnected through a resistor 147, and thereby maintained at the same potential.
A serial circuit of resistors 143 and 144 is connected between a power supply terminal 121 and a ground terminal 122, whereby the connection point between the resistors 143 and 144 serves as a reference voltage terminal 123. The gate electrode of the field effect transistor 131 is connected through a resistor 145 to the reference voltage terminal 123. The source electrode of the field effect transistor 132 is connected directly to the reference voltage terminal 123.
A reference voltage generation circuit is constructed from the resistors 143 and 144 connected between the power supply terminal 121 and the ground terminal 122. Capacitors 151-154 are inserted for eliminating DC components. The resistors 141, 142, 145, 146 and 147 have high resistance values. The control terminal 124 is used for controlling the operation state of the switch circuit.
The circuit of resistors 143 and 144 constituting the reference voltage generation circuit have the same resistance value. Thus, when a power supply voltage Vdd is provided to the reference voltage generation circuit, the voltage Vref outputted from the reference voltage terminal 123 equals to Vdd/2.
For example, in FIG. 6, when the power supply voltage Vdd provided to the power supply terminal 121 is 3 V, and when the ground terminal 122 is grounded, the reference voltage Vref generated in the reference voltage terminal 123 by the reference voltage generation circuit equals to 1.5 V. In this case, when the control voltage Vc provided to the control terminal 124 is 0 V, the drain electrode and the source electrode of the field effect transistor 131 serving as a switching element are provided with a voltage of 0 V, while the gate electrode thereof is provided with a voltage of 1.5 V. Further, the drain electrode and the source electrode of the field effect transistor 132 serving as a switching element are provided with a voltage of 1.5 V, while the gate electrode thereof is provided with a voltage of 0 V.
The threshold voltages Vth of the field effect transistors 131 and 132 are assumed to be −0.7 V. In the field effect transistor 131, the gate electrode is at a potential exceeding 0 V which is higher than those of the source electrode and the drain electrode. This results in a low impedance between the source electrode and the drain electrode of the field effect transistor 131. Thus, the field effect transistor 131 is ON. In contrast, in the field effect transistor 132, the gate electrode is at a potential lower than the potential lower than those of the source electrode and the drain electrode by the threshold voltage Vth of the field effect transistor 132. This results in a high impedance between the source electrode and the drain electrode of the field effect transistor 132. Thus, the field effect transistor 132 is OFF.
In this state, when a high frequency signal is inputted through the signal input terminal 125, the high frequency signal is transmitted through the field effect transistor 131 having a low impedance, and then outputted through the signal output terminal 127. Further, the high frequency signal inputted through the signal input terminal 125 is blocked by the field effect transistor 132 having a high impedance, and hence not outputted through the signal output terminal 128. As a result, the high frequency signal inputted through the signal input terminal 125 is outputted from the signal output terminal 127.
Next, in FIG. 6, when the power supply voltage Vdd provided to the power supply terminal 121 is 3 V, and when the ground terminal 122 is grounded, the reference voltage Vref generated in the reference voltage terminal 123 by the reference voltage generation circuit equals to 1.5 V. In this case, when the control voltage Vc provided to the control terminal 124 is 3 V, the drain electrode and the source electrode of the field effect transistor 131 serving as a switching element are provided with a voltage of 3 V, while the gate electrode thereof is provided with a voltage of 1.5 V. Further, the drain electrode and the source electrode of the field effect transistor 132 serving as a switching element are provided with a voltage of 1.5 V, while the gate electrode thereof is provided with a voltage of 3 V.
The threshold voltages Vth of the field effect transistors 131 and 132 are assumed to be −0.7 V. In the field effect transistor 131, the gate electrode is at a potential lower than the potential lower than those of the source electrode and the drain electrode by the threshold voltage Vth of the field effect transistor 131. This results in a high impedance between the source electrode and the drain electrode of the field effect transistor 131. Thus, the field effect transistor 131 is OFF. In contrast, in the field effect transistor 132, the gate electrode is at a potential exceeding 0 V which is higher than those of the source electrode and the drain electrode. This results in a low impedance between the source electrode and the drain electrode of the field effect transistor 132. Thus, the field effect transistor 132 is ON.
In this state, when a high frequency signal is inputted through the signal input terminal 125, the high frequency signal is transmitted through the field effect transistor 132 having a low impedance, and then outputted through the signal output terminal 128. Further, the high frequency signal inputted through the signal input terminal 125 is blocked by the field effect transistor 131 having a high impedance, and hence not outputted through the signal output terminal 127. As a result, the high frequency signal inputted through the signal input terminal 125 is outputted from the signal output terminal 128.
According to the circuit configuration of the high frequency switch of FIG. 6, the value of the control voltage provided to the control terminal 124 can control the high frequency switch using the MES FETs. Here, positive voltage values are sufficient for this control voltage.
FIG. 7 shows the relation between the control voltage Vc of the SPDT switch circuit of FIG. 6 and the insertion loss between the signal input terminal 125 and the signal output terminal 127 or 128. In FIG. 7, the state that the insertion loss is 0 dB or the like is defined as a conductive state, while the state that the insertion loss is −20 dB or lower is defined as a cut-off state.
In FIG. 7, in the region where the control voltage Vc and the reference voltage Vref are in the relation Vc<Vref−|Vth|, the gate electrode of the field effect transistor 131 is at a potential higher than those of the source electrode and the drain electrode thereof. Thus, the field effect transistor 131 is ON. Further, the gate electrode of the field effect transistor 132 is at a potential lower than the potential lower than those of the source electrode and the drain electrode thereof by the threshold voltage Vth of the field effect transistor 132. Thus, the field effect transistor 132 is OFF. At this time, a high frequency signal inputted through the signal input terminal 125 is transmitted through the field effect transistor 131, and then outputted from the signal output terminal 127.
In contrast, in the region where the control voltage Vc and the reference voltage Vref are in the relation Vc>Vref+|Vth|, the gate electrode of the field effect transistor 131 is at a potential lower than the potential lower than those of the source electrode and the drain electrode thereof by the threshold voltage Vth of the field effect transistor 131. Thus, the field effect transistor 131 is OFF. Further, the gate electrode of the field effect transistor 132 is at a potential higher than those of the source electrode and the drain electrode thereof. Thus, the field effect transistor 132 is ON. At this time, a high frequency signal inputted through the signal input terminal 125 is transmitted through the field effect transistor 132, and then outputted from the signal output terminal 128.
Nevertheless, in the region where the control voltage Vc is in the range of Vref−|Vth|<Vc<Vref+|Vth|, the insertion loss of the field effect transistor 131 or 132 is in the range between 0 dB and −20 dB, whereby the ON/OFF states of the field effect transistors 131 and 132 are not certain. This indicates that a path between the signal input terminal 125 and the signal output terminal 127 or 128 cannot be selected in the SPDT switch circuit. That is, there is a voltage range not available in the setting of the control voltage Vc for controlling the SPDT switch circuit. This range is labeled an “uncertain region” in FIG. 7.
For example, in case that the power supply voltage Vdd is 3V, that the threshold voltages of the field effect transistors 131 and 132 are −0.7 V, and that the range of the control voltage Vc is 0 V through 3 V, the range between 0.8 V and 2.2 V (1.4 V width) is not available for the control voltage Vc. Since the range of the control voltage Vc is 0 V through 3 V, approximately a half of the range is not available for the control voltage Vc.
Described below is a high frequency amplifier circuit supporting a plurality of communication schemes such as PDC and W-CDMA. FIG. 8 is a detailed circuit block diagram of the high frequency amplifier circuit 104 of FIG. 5.
As shown in FIG. 8, in the high frequency amplifier circuit 104, a high frequency signal inputted through a signal input terminal 181 is provided through an impedance matching circuit 182 for performing impedance transformation, to a gain control circuit 183, whereby gain attenuation is performed on the high frequency input signal. The amount of attenuation in the gain control circuit 183 is controlled by the setting of the voltage value in a control terminal 189. The output signal of the gain control circuit 183 is provided to an amplifier 184, and thereby amplified. The output signal of the amplifier 184 is provided through an impedance matching circuit 185 for performing impedance transformation, to an amplifier 186, and thereby amplified. The output signal of the amplifier 186 is provided through an impedance matching circuit 187 for performing impedance transformation, to a signal output terminal 188.
Described below is the use of the high frequency amplifier circuit 104 of FIG. 8 in a high frequency circuit block of a communication terminal supporting a plurality of communication schemes. Here, the frequency and the output power used in the communication terminal are different in PDC scheme and in W-CDMA scheme. Thus, the circuit configuration of the high frequency amplifier circuit needs to be determined such as to meet the severer requirement in the high frequency characteristics of the communication schemes. For example, considered below is the situation that the output power used in the high frequency amplifier circuit is different in these communication schemes. In general, in a high frequency amplifier circuit, a higher output power requires a higher operation current in the high frequency amplifier circuit. Thus, the high frequency amplifier circuit needs to be designed such as to meet the power requirement of the higher output power.
A first problem is that in the prior art high frequency switch, the setting range of the control voltage of the high frequency switch depends on the power supply voltage of the high frequency switch, and that the setting range of the control voltage of the high frequency switch is narrow.
The reason is that there is a control voltage range where the ON/OFF state of the field effect transistors 131 or the field effect transistor 132 constituting the switch circuit is not determined. For example, in case that the power supply voltage Vdd is 3V, that the threshold voltages of the field effect transistors 131 and 132 are −0.7 V, and that the range of the control voltage Vc is 0 V through 3 V, the range between 0.8 V and 2.2 V (1.4 V width) is not available for the control voltage Vc. Since the range of the control voltage Vc is 0 V through 3 V, approximately a half of the range is not available for the control voltage Vc.
Further, the threshold voltage of the field effect transistor is almost constant independently of the power supply voltage. Thus, when the power supply voltage of the high frequency switch decreases, the power supply voltage of the reference voltage terminal also decreases, whereby the available setting range of the control voltage becomes narrower.
A second problem is that in the configuration of a high frequency amplifier circuit supporting a plurality of communication schemes, the operation current increases in the high frequency amplifier circuit.
The reason is that when the high frequency characteristics such as the output power required in the communication terminal is different in each communication scheme, the circuit configuration of the high frequency amplifier circuit needs to be determined such as to meet the severer requirement in the high frequency characteristics of the communication schemes. Thus, in the operation mode of the communication scheme using the lower output power, the operation current flows excessively.
In particular, a portable telephone terminal of W-CDMA scheme needs to communicate with a base station continuously during the telephone call, and thereby tends to consume a higher power. Accordingly, in order that a longer usable time is obtained with a battery having a limited capacity, the operation current is preferably reduced in the operation mode of the communication scheme using the lower output power. Further, this needs to be implemented without conflicting with the size and weight reduction.